Ascend 950: A Milestone for Domestic AI Compute

In March 2026, Huawei unveiled the Ascend 950PR accelerator card and the Atlas 350 server at MWC Barcelona and the Huawei China Partner Conference, marking a new phase for the Ascend AI chip ecosystem. As the core part of Huawei’s roadmap – “one generation per year, doubling compute power” – the launch of the Ascend 950 series goes beyond mere parameter stacking. It reflects Huawei’s strategic shift in the face of global supply chain challenges: instead of obsessively chasing absolute leadership in single‑card peak performance, it pursues a path of systemic innovation through refined architecture, scenario‑specific design, and revolutionary SuperNode technology.

1. Ascend 950 Architecture: Two Chips, Precision Targeting

The Ascend 950 series boldly abandons the traditional “one‑size‑fits‑all” design, adopting a strategy of “same die core + differentiated configuration” that yields two models for different scenarios: the 950PR and the 950DT. Both chips share the same 950 core architecture, differing only in the accompanying self‑developed HBM memory and software tuning, thereby achieving precise balance between cost and performance.

1.1 Ascend 950PR

Positioned to accelerate AI inference and recommendation workloads, especially the prefill phase of large language model inference, it is the first Ascend chip to use Huawei’s self‑developed high‑bandwidth memory. Key technical highlights include:

• Self‑developed HBM (HiBL 1.0): 112GB (standard card) / 128GB (chip specification) capacity, 1.4 TB/s bandwidth, balancing cost control and performance.

• Full embrace of low‑precision computing: Supports FP8, MXFP8, HIF8, and FP4, with FP8 compute of 1 PFLOPS and FP4 compute up to 2 PFLOPS, significantly increasing throughput.

• HiF8 self‑developed format: Huawei’s proprietary low‑precision format that retains the efficiency of FP8 while achieving accuracy very close to FP16, striking a clever balance between compute power and precision.

• Atlas 350 accelerator card: 600W power consumption, 1.56 PFLOPS at FP4 precision, 60% faster multi‑modal generation.

1.2 Ascend 950DT

As the workhorse for training and the decode phase of inference, the 950DT targets the high‑concurrency memory access demands of large‑model training. It employs a high‑performance version of the self‑developed HBM (HiZQ 2.0), with memory capacity increased to 144GB and interconnect bandwidth up to 4 TB/s. It is scheduled for launch in the fourth quarter of 2026.

1.3 Architecture Evolution: From SIMD to SIMD/SIMT Dual Mode

Based on the DaVinci architecture, the Ascend 950 series introduces a dual SIMD/SIMT programming model. The 910C era’s SIMD architecture focused on vector computing – extremely efficient for processing continuous data like matrix multiplications in training – but was less effective for the fragmented data processing that occurs during the inference decode phase. The 950 series adds a SIMT model to flexibly schedule fragmented data, reducing the memory access granularity from 512 bytes to 128 bytes and improving discrete memory access efficiency by 4 times, achieving seamless switching between “large‑block vector pipeline processing” and “flexible scheduling of fragmented data”.

2. Evolution Across Generations: From Follower to Contender

The evolution of Huawei’s Ascend AI chips follows a clear path from “scattered deployment” to “systematic strength”.

1. Ascend 310 & 910: The Foundation Era
   Early Ascend 310 (12nm/8W) focused on edge computing, while Ascend 910 (7nm/256 TFLOPS@FP16) served as the main cloud training chip, establishing the basic DaVinci architecture paradigm.

2. Ascend 910C: The Scaling Springboard
   The 910C is not an entirely new chip design but uses a dual‑die packaging of two Ascend 910B chips to double compute power, reaching ~800 TFLOPS (FP16). It quickly filled the domestic gap for training hundred‑billion‑parameter models and enabled large‑scale deployment through the Atlas 384 SuperNode.

3. Ascend 950: The Scenario‑Driven Turning Point
   Facing the cost‑sensitive inference market, the 950 series no longer blindly stacks general‑purpose compute. Instead, through scenario segmentation and self‑developed HBM, it is the first Ascend generation to compete head‑to‑head with NVIDIA’s mid‑to‑high‑end products.

4. Ascend 960/970: Future Compute Commitments
   On Huawei’s roadmap, the 960 and 970 will continue the “doubling specs” philosophy. The 970 will further adopt N+3 process technology and a four‑die package design, improving energy efficiency by >30% over the 910C, targeting trillion‑parameter Mixture of Experts (MoE) architectures.

3. Comprehensive Comparison with NVIDIA GPUs

3.1 Single‑Card Core Specs Comparison

3.2 Gaps and Breakthroughs

• Inference: Approaching or even locally surpassing
  In inference/recommendation and large‑model inference, the Ascend 950PR performs admirably. It reaches 2.87× the FP4 low‑precision performance of the NVIDIA H20. While its memory bandwidth is only 1.4 TB/s, through the trade‑offs of self‑developed HBM and the HiF8 precision format, it already offers attractive cost‑performance for specific commercial scenarios.

• Training: Still catching up
  In flagship AI training, the Ascend 950 still lags behind the NVIDIA H200. The core differences lie not only in single‑card floating‑point compute (FP16/BF16) but also in the memory bandwidth gap (4 TB/s vs. 4.8 TB/s). However, without being affected by export restrictions, its overall performance already far exceeds the China‑specific H20.

4. Systemic Strategy: The SuperNode Architecture – The Key to Overtaking on a Curve

If there is a generation gap in single‑card performance between the Ascend 950 and the NVIDIA B200, then at the system‑level compute scale, Huawei has charted a differentiated path with its “SuperNode” technology.

4.1 Connecting Tens of Thousands of Cards, Winning Through Scale

Under the constraint of advanced process limits, Huawei has chosen to break through via the revolutionary SuperNode architecture. The Atlas 950 SuperNode supports high‑speed interconnection of up to 8,192 Ascend 950DT chips, delivering a total compute power of 8 EFLOPS at FP8 precision, with interconnect bandwidth soaring to 16.3 PB/s. These figures are globally leading among similar products and demonstrate Huawei’s deep accumulated strength in systems engineering.

4.2 The “Spirit Interconnect” Protocol: Redefining Interconnection

Huawei’s self‑developed “Spirit Interconnect” protocol is the key. Traditional solutions are constrained by long‑distance, high‑reliability connectivity and high‑bandwidth, low‑latency transmission. By introducing high‑reliability mechanisms at every layer of the interconnect protocol, Huawei has achieved a 100‑fold improvement in optical interconnect reliability and an interconnect distance exceeding 200 meters, paving the way for building tens‑of‑thousands‑card clusters.

5. Software Ecosystem and Developer Support: From Passive Porting to Proactive Collaboration

Beyond hardware, the ecosystem remains a major challenge for Ascend. NVIDIA’s CUDA ecosystem, built over many years, has created a high migration barrier.

However, the situation is accelerating in the other direction. As leading AI companies like DeepSeek engage in deep collaboration with Huawei, cracks are beginning to appear in the ecosystem barrier.

• Deep co‑optimization example: When the DeepSeek team fully migrated their models from NVIDIA A100/H800 to the Huawei Ascend 950PR, they did not just do simple driver porting. Instead, targeting Ascend’s hardware characteristics, they deeply designed and tuned their unique mHC sparse activation architecture – under Ascend’s limited HBM bandwidth, activating only the subset of expert layers most relevant to the current task to substantially reduce unnecessary memory I/O. This ultimately allowed the Ascend 950PR’s peak BF16 compute (~900 TFLOPS) to be fully realized in real‑world scenarios.

• Open‑sourcing the software stack: Huawei announced the opening of the CANN compiler interface and fully open‑sourced toolchains and large models such as MindSpore and openPangu, lowering development barriers.

• Day‑0 native adaptation: When DeepSeek‑V4 was released, Huawei Ascend achieved “Day‑0 adaptation” – the chip was fully compatible on the very day of the model’s release. This reflects a “two‑way奔赴” (synergistic co‑evolution) relationship between cutting‑edge models and domestic software/hardware.

6. Summary and Outlook

The birth of the Ascend 950 marks a new phase in Huawei’s AI compute strategy: from “passive catch‑up” to “proactively defining scenarios”. It follows a pragmatic technical path: instead of obsessing over single‑card peak metrics, it maximizes total compute output under process constraints through architectural innovation, system‑level interconnect, and precise scenario targeting.

As AI competition escalates from a single‑dimensional contest of single‑card performance to a systemic battle of tens‑of‑thousands‑card clusters, Huawei, with its “SuperNode + Spirit Interconnect” technology, has found its own main battleground. As Xu Zhijun said at the Huawei Connect Conference: “China’s semiconductor manufacturing technology will remain in a state of backwardness for a considerable period.” Choosing systemic innovation rather than point breakthroughs under such constraints may be the most pragmatic and effective path for domestic AI compute. The Ascend 950 is not the end of the answer, but a key node where the problem‑solving approach turns.