​ Supernodes Cross the Line: The Unit of Compute Competition Shifts from “One Card” to “One Computer”

Over the past week, the most noteworthy change in the compute sector has not been at the model layer, nor in the single-point specifications of chips, but at a more “hardware” level: supernodes are moving from technical proposals to scaled delivery, and the basic unit of compute competition is beginning to upgrade from “one card” to “one logical computer.” On October 15, the first 1,024-card Ascend Atlas 950 SuperPoD liquid-cooled supernode was officially lit up and simultaneously completed zero-day adaptation for StepFun’s Step 5 Preview, marking what is described as the first deployment of the industry’s largest supernode product. Seven days later, on October 22, a research report by China Securities gave a clearer stage judgment: domestic and international vendors are releasing supernode products intensively, the industry has officially moved from solution validation to the stage of scaled delivery, and “2026 is expected to be the first year of volume ramp-up for domestic supernodes.”

Taken together, these two signals explain the situation better than any single product launch. Lighting up means “it can run”; setting the tone means “it is time for volume delivery.” Supernodes are no longer concept prototypes on exhibition floors, nor customized validation in a handful of projects; they are becoming a standard delivery form of compute infrastructure. And once scaled delivery begins, the yardstick of competition shifts from “whose single card is stronger” to “who can make more cards work like a single machine and make the economics work for customers.”

I. The Bottleneck Is Not “Compute” but “Moving Data”

To understand why supernodes are taking off at this point, we first need to understand what has changed in large-model workloads. The basic unit of a traditional AI cluster is individual servers: chips within a server are tightly connected, while servers exchange data over ordinary networks. When model scale was small, this structure was sufficient. But as models move toward MoE, long context, and agents, the pressure spreads from pure “computation” to communication, memory, and stability.

MoE models need to continuously dispatch tasks to different expert networks, and communication efficiency among experts directly determines how fast the model runs; long context generates large amounts of KV Cache, continuously occupying GPU memory and memory bandwidth; an agent completing a complex task may go through hundreds of rounds of inference, tool calls, feedback, and replanning, repeatedly amplifying system latency and stability requirements. If data cannot move fast enough between chips and servers, even the highest-compute chips can only wait. A factory may have a large number of high-speed machines, but if materials move too slowly between workshops, the machines’ peak capacity may be high while the actual output of the entire production line remains low—this is exactly the “moving” problem that supernodes aim to solve.

Their core approach is to use higher-bandwidth, lower-latency scale-up interconnect to organize chips, GPU memory, and memory originally scattered across different servers into the same compute domain, so that the upper-layer model sees not a bunch of independent servers communicating over a network, but something closer to a computer with enormous compute and memory. The specifications Huawei gave for the Ascend 950 supernode are representative: a single cluster of 1,024 Ascend NPUs, 256 TB globally unified memory addressing, TB-level interconnect bandwidth between NPU cards, end-to-end communication latency as low as 3 microseconds, and 1,024 cards can directly access each other without complex protocol conversion and switch relay. The entire cluster is logically equivalent to “one supercomputer,” with compute scaling growing almost linearly with scale. Iluvatar CoreX put it more concisely for the Tiangai 300 IXL144: it forms a high-bandwidth domain with unified memory semantics for 144 GPUs, keeping high-frequency All-to-All interactions within the rack and reducing cross-rack waiting.

This means the value of a supernode cannot be simply measured as “per-card compute multiplied by the number of cards.” It changes the production function of effective compute: with the same chips, under different interconnect architectures, memory addressing, and scheduling policies, the actual throughput that can be released may differ by a large margin. The China Securities research report points in the same direction: by expanding the scale-up interconnect domain, unifying memory addressing, and improving in-rack interconnect efficiency, supernodes use systems engineering capability to break through the cross-node communication bottleneck of traditional eight-GPU servers, and have significant advantages in compute utilization, interconnect bandwidth, throughput, latency, MoE adaptation, and per-card effective throughput.

II. Three Routes, Two Densities, One Common Direction

The密集 flow of information this week also shows that domestic supernodes have not converged on a single technical route. Instead, under the common goal of “packing more cards into the same high-speed collaboration zone,” they have taken differentiated paths.

Huawei takes a full-stack vertically integrated route. The Ascend 950 supernode is based on the Lingqu high-speed interconnect architecture and supernode technology system, putting unified memory addressing, the Lingqu bus, and high-density liquid cooling into the same system design. The 1,024-card fully liquid-cooled supernode brings both compute cabinets and interconnect cabinets into the liquid-cooling system at the hardware level, and at the software level simultaneously completes zero-day adaptation for Step 5 Preview. Targeting sparse MoE architectures and long-context characteristics, it carries out full-stack hardware-software co-design across operator fusion, communication optimization, and framework scheduling. The official statement is that “inference performance catches up with advanced overseas compute levels.” This route is closer to the logic of NVIDIA’s GB200/GB300 system-level delivery: chips, interconnect, racks, cooling, and software stack are defined by the same system, and what is delivered to the customer is a relatively closed but highly coordinated system.

Iluvatar CoreX takes a high-density single-rack and ecosystem-compatible route. The Tiangai 300 IXL144 integrates 144 GPUs and 18 CPUs in a single rack, with about 10.1 TB of GPU memory, and is described as the industry’s highest-density single-rack GPU supernode. But what Iluvatar CoreX emphasizes is not just density. It adopts a single-rack form close to standard rack specifications and can directly enter existing data centers when power distribution, floor loading, and cooling conditions match, without requiring dedicated data centers, large-scale renovation, and long cycles like some purpose-built whole-rack supernodes. At the same time, it is compatible with the CUDA ecosystem, supporting customers in reusing existing models, mainstream frameworks, and development experience, lowering migration costs. This means Iluvatar CoreX’s route leans more toward “lowering the deployment threshold for supernodes,” allowing existing data centers to enter supernode form incrementally.

Lanxin Computing, by contrast, enters from the instruction set architecture level. On October 19–20, Lanxin Computing released its AI-compute and communication integrated supernode at the RISC-V China Summit, based on the LX500, the world’s first mass-produced RISC-V + AI compute-communication integrated server CPU, extending AI compute capability from single chips and servers to clustered compute infrastructure, covering scenarios from single-machine inference to cluster training. This route is currently small in scale, but its signal significance is that system-level competition in supernodes is attracting participants from different architecture camps; RISC-V is no longer just an alternative for edge and endpoint, but is beginning to probe cluster-level compute infrastructure.

The three routes also clearly diverge in density: Huawei’s 1,024 cards are the scale benchmark for cluster-level supernodes; Iluvatar CoreX’s 144-card single rack is the benchmark for density and deployment convenience; and Lanxin proposes another system combination from the architectural level of CPU-AI integration. But they point in the same direction: competition in supernodes is essentially competition over “the right to define the system”—whoever defines how chips connect, how memory is addressed, how racks are powered and cooled, and how the software stack is scheduled determines how much effective compute the system can ultimately release.

III. “System Economic Efficiency” Becomes the New Yardstick

As supernodes move from solution validation to scaled delivery, they bring another change that is easily obscured by technical specifications: the evaluation standard is shifting from “is performance high enough” to “is system economic efficiency worthwhile.”

A remark by Zou Xuan, vice president of Iluvatar CoreX, is worth noting: “A supernode is not a single product but a systems engineering project; in the end, what is compared is system economic efficiency.” This statement is highly relevant to the current stage. Supernodes improve effective compute through a larger interconnect domain and unified memory addressing, but they also bring higher per-rack power density, more complex liquid-cooling and power-supply requirements, longer deployment cycles, and higher initial investment. If only peak compute is considered, supernodes are almost inevitably superior to traditional eight-GPU servers; but if data center renovation costs, power capacity expansion cycles, liquid-cooling O&M complexity, and actual utilization are taken into account, the conclusion is not necessarily so linear.

An estimate from Iluvatar CoreX provides a reference: the cost per million effective tokens can be reduced by 40% compared with mainstream international solutions. The statistical basis of this figure needs to be treated with caution, because it depends on specific scenarios, workload types, and comparison baselines and cannot be directly generalized to all inference tasks. But its directional significance is clear: the commercial rationality of supernodes must ultimately rest on “effective output per unit,” not “peak compute per unit.” This also explains why Iluvatar CoreX chose to emphasize “close to standard racks, scalable in steps, and compatible with the CUDA ecosystem”—reducing deployment friction is itself part of system economic efficiency.

The economic-efficiency logic of Huawei’s 1,024-card supernode is different. It targets high-concurrency inference and training of trillion-parameter large models, as well as frontier scenarios such as million-token long context and multimodal agents. Such workloads are extremely sensitive to communication latency and memory capacity; cross-node communication overhead in traditional clusters may eat up a considerable portion of compute, while the supernode compresses “waiting for communication” time as much as possible by bringing 1,024 cards into a unified memory semantic domain. For such scenarios, whether the supernode premium is worth it depends on how sensitive the workload is to the communication bottleneck. The heavier the workload, the finer the parallelism granularity, and the more frequent the All-to-All interactions, the more obvious the supernode’s relative advantage.

Therefore, the key question in the scaled delivery stage is not “will supernodes replace traditional clusters,” but “under what workloads, what data center conditions, and what cost structures are supernodes more cost-effective than traditional clusters.” There is no unified answer to this question, but raising it itself marks an increase in industry maturity: from proving technical feasibility to proving commercial feasibility.

IV. What Scaled Delivery Means

China Securities defines 2026 as “the first year of volume ramp-up for domestic supernodes” and notes that server systems, switch chips, switches, and connectors in the industrial chain are expected to benefit first, while PCB, liquid cooling, power supplies, CPUs, and domestic compute chips will also continue to benefit as supernode penetration rises. The essence of this judgment is that the scaling of supernodes will pull a longer and deeper industrial chain than traditional eight-GPU servers.

The value of traditional servers is mainly concentrated in motherboards, CPUs, GPUs, and ordinary network equipment. Supernodes shift the center of value toward interconnect, cooling, power supply, and system integration. Liquid cooling has changed from “optional” to “mandatory” because the per-rack power of high-density supernodes has exceeded the economical carrying range of air cooling. Specifications for switch chips and connectors are pushed higher because the larger the scale-up interconnect domain, the more demanding the requirements for bandwidth, latency, and signal integrity. Power supplies and distribution systems need to be redesigned because the increase in per-rack power density cannot be solved by simply adding a few power modules linearly. PCB layer counts, materials, and process requirements will also rise with high-speed signal density. The benefits to these links are not conceptual “good news for the compute industrial chain,” but structural demand brought by changes in the physical form of supernodes.

A deeper change lies in the delivery model. The delivery of traditional compute clusters is largely “selling servers”: customers receive a batch of machines and handle networking, tuning, and cross-node communication themselves. Supernode delivery is closer to a “turnkey system”: the supplier is responsible for interconnect topology, memory addressing, cooling solutions, software stack adaptation, and throughput under actual workloads. Huawei’s 1,024-card supernode completing zero-day adaptation for Step 5 Preview at the same time it was lit up is a typical signal—what the customer buys is not a bare hardware cluster but a compute foundation that has already undergone system-level optimization for the target model. This delivery model places higher demands on suppliers’ systems engineering capability, but once it works, customer stickiness and switching costs will also rise significantly.

From a policy perspective, scaled delivery of supernodes is also consistent with the direction of “expanding and upgrading computing facilities.” In the “15th Five-Year Plan for the Development of the Information and Communications Industry” released in September, MIIT proposed that by 2030 intelligent compute scale should grow more than fivefold compared with 2025 and listed “capacity expansion and quality improvement” as a key task; computing facilities have been included in the national “six networks” strategic infrastructure system. Supernodes are precisely a concrete carrier of “quality improvement” at the hardware level: they do not simply increase the number of cards but, through system-level interconnect and memory addressing, make the same number of cards produce more effective compute. Against the backdrop of export controls restricting access to high-end overseas chips, the scaling of domestic supernodes also has an additional strategic meaning: when catching up on single-card performance takes time, using system-level coordination to raise the effective compute of multiple cards is a more realistic efficiency path.

V. Concluding Remarks: From “Building Compute” to “Delivering Compute Systems”

In recent years, the main narrative of the compute industry has been “build”: build larger data centers, buy more cards, and lay wider compute networks. The密集 progress of supernodes this week suggests that a different stage is arriving: the focus of competition is shifting from “how much to build” to “what kind of system to deliver, and how much that system can produce under real workloads.”

The lighting up of the 1,024-card Ascend 950 supernode proves that domestic supernodes have reached the industry’s forefront in scale; Iluvatar CoreX’s 144-card single-rack solution proves that supernodes do not all have to be premised on “dedicated data centers + large-scale renovation”; Lanxin’s RISC-V route proves that participants in system-level innovation are diversifying; and China Securities’ judgment of “scaled delivery” pushes the issue from technical validation to industrial realization. The next focus of observation is not how many more cards have been lit up, but: the utilization, throughput, and per-token cost of already delivered supernodes under real MoE and agent workloads; whether the engineering bottlenecks of liquid cooling and power supply are being absorbed at scale; whether customers are willing to pay a premium for “system-level delivery”; and whether domestic supernodes can find a sustainable balance between CUDA ecosystem compatibility and independent software stacks.

The significance of supernodes crossing the line is not that they eliminate a particular server form factor, but that they change the unit of measurement in compute competition from “cards” to “systems.” When the unit of competition changes, the yardstick for measuring success changes with it. In the next round of compute competition, what matters is not who owns more chips, but who can organize more chips into a truly usable computer and make the economics work for customers.